1. Field of the Invention
The present invention generally relates to a test signal generating circuit for generating a test signal for testing logic circuits. More particularly, the present invention relates to a test signal generating circuit which is so arranged as to be capable of delaying the timing at which a test signal is produced for a given time and varying the waveform of the test signal.
2. Description of the Prior Art
In the hitherto known apparatus for testing ICs, a plurality of waveform shaping units are employed for generating logic waveforms of test patterns to be applied to individual pins of an IC device under test, wherein the basic timing signals to be supplied to the plural waveform shaping units are collectively produced by a single timing signal generating unit. With such arrangement, it is difficult or even impossible to assure acceptable timing accuracy for the output signals of the individual waveform shaping units because of non-uniformity in the delay times involved by logic elements of the plural waveform shaping units, cross-talk occurring between the logic signals and the like factors.